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AS3955 データシート(PDF) 62 Page - ams AG

部品番号 AS3955
部品情報  NFC Forum Compliant Dynamic Tag
PDF  102 Pages
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メーカー  AMSCO [ams AG]
ホームページ  http://www.ams.com
Logo AMSCO - ams AG

AS3955 データシート(HTML) 62 Page - ams AG

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Page 62
ams Datasheet
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[v1-04] 2016-Feb-03
AS3955 − Detailed Description
Writing and Reading of EEPROM Through SPI
EEPROM data can be read and written also through SPI
interface. Due to possible conflict with the RFID interface
additional arbitration bit can be set (IC_CFG0) in order to set
the priority access to the EEPROM access. If EEPROM write
operation is terminated due to higher priority of the RF an I_
acc_err (Interrupt Register 1) IRQ is sent. The description is
referring to following case when an EEPROM write operation is
triggered via SPI / I²C and bit arbit_mod (EEPROM, IC_CFG0,
bit3) is set to 1 which means that RF has priority over SPI when
accessing EEPROM. In this case EEPROM via SPI / I²C write will
be terminated and IRQ I_acc_err is triggered if tags enters RF
field and EEPROM is needed for RF initialization, EPROM read or
write is issued via RF.
Word Address Byte
Both EEPROM modes (Read and Write) use Word Address byte
to define the address of the EEPROM word which is accessed.
Seven MSB bits of the Address Byte are used to define the
address; while the last bit is don’t care (it is used to synchronize
EEPROM access).
Figure 63:
EEPROM Block Address Byte
EEPROM Write
In order to program an EEPROM block, six bytes shall be sent
(mode byte, block address byte and 4 bytes of data, all of them
MSB first). Actual EEPROM programming is started with rising
/SS edge signal which terminates the EEPROM Write command.
EEPROM Read
In order to read data from EEPROM, first a mode byte is sent,
followed by the block address byte (MSB first). Then one or more
blocks of data with address auto-incrementing (packets of 4
bytes) are transferred to MISO output, also MSB first. MOSI is
sampled at the SCLK falling edge; data to be read from AS3955
EEPROM is driven to MISO pin on SCLK rising edge and is
sampled by the master at the SCLK falling edge. In case the
block on the defined address does not exist, all 0 data is sent to
MISO.
Please note that SCLK frequency should not exceed 1MHz
during EEPROM Read (limited by EEPROM read access time).
B7
B6
B5
B4
B3
B2
B1
B0
EEPROM Block Address
WA6
WA5
WA4
WA3
WA2
WA1
WA0
x



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