AS3955 datasheet(82/102 Pages) AMSCO

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[v1-04] 2016-Feb-03

AS3955 − Register Description

Figure 93:

Interrupt Register 0

Note(s):

1. Power-up and Set Default command set the content of this register to 0. After Interrupt Register has been read, its content is set

again to 0.

Figure 94:

Interrupt Register 1

Address 0Ah: Interrupt Register 0

Bit

Name

Function

Type

7I_pu

Power-up IRQ. Interrupt is triggered at each power up (RF or battery),

when chip is already powered and RF field appears and after Go To

Sleep, Go To Sense, Go To Sense / Sleep and Set Defaultcommand

I_wu_a

Wake-up IRQ at entry in SELECTED state

I_slp

IRQ due to reception of SLP_REQ command

I_eew_rf

PCD has updated the content of the data area

I_eer_rf

PCD has read the content of the data area

2I_rxe

IRQ due to End of Receive. Applicable when receive frame is put in

buffer

1I_txe

IRQ due to End of Transmission. Applicable when data from buffer is

sent

I_xrf

Exit RF field IRQ

Address 0Bh: Interrupt Register 1

Bit

Name

Function

Type

7I_rxs

IRQ due to Start of Receive. Applicable when receive frame is

put in buffer

I_frm_err

Lower layer error (broken byte, wrong bit coding sequence) / In

case of error the receive data is still put in buffer, error IRQ is

additionally sent

5I_par_err

Parity error / In case of error the receive data is still put in buffer,

error IRQ is additionally sent

4I_crc_err

CRC error / In case of CRC error the receive data is still put in

buffer, error IRQ is additionally sent

I_bf_err

Buffer error (overflow/underflow). See Buffer Status Register 2

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