STM8L151C2 datasheet(16/123 Pages) STMICROELECTRONICS

16 / 123 page

Functional overview

STM8L151x2, STM8L151x3

16/123

DS7204 Rev 11

Architecture and registers

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Harvard architecture

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3-stage pipeline

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32-bit wide program memory bus - single cycle fetching most instructions

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X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

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8-bit accumulator

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24-bit program counter - 16 Mbyte linear memory space

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16-bit stack pointer - access to a 64 Kbyte level stack

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8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

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20 addressing modes

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Indexed indirect addressing mode for lookup tables located anywhere in the address

space

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Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

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80 instructions with 2-byte average instruction size

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Standard data movement and logic/arithmetic functions

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8-bit by 8-bit multiplication

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16-bit by 8-bit and 16-bit by 16-bit division

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Bit manipulation

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Data transfer between stack and accumulator (push/pop) with direct stack access

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Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2

Interrupt controller

The low-density STM8L151x2/3 feature a nested vectored interrupt controller:

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Nested interrupts with 3 software priority levels

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32 interrupt vectors with hardware priority

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Up to 40 external interrupt sources on 11 vectors

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Trap and reset interrupts

STM8L151C2 データシート(PDF) 16 Page - STMicroelectronics

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