MPC7410EC datasheet(52/56 Pages) NXP

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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

Document Revision History

0.3

—

Added 3.3 V support on the processor bus (BVSEL).

Table 7—update typical and maximum power numbers for full-on mode in. Removed note 4.

Reworded notes 2 and 3.

Table 9, Note 2—removed reference to application note.

Figure 17—corrected side view datum A to be datum C.

Section 1.8.7—added CI and WT to transfer attribute signals requiring pull-ups.

Section 1.8.7—added 1-k

Ω pull-up recommendation to GBL when GBL is not connected.

Table 2— added pull-down resistance necessary for internally pulled-up voltage select pins. Added

3.3-V support for BVSEL.

Table 13—added note 14 for BVSEL, L2VSEL, and TRST pins to address pull-down resistance

necessary for these internally pulled-up pins to recognize a low signal.

Table 6—lowered 2.5 V CVIH from 2.2 to 2.0 V to be compatible with VOH of the MPC107. Added

support for 3.3-V processor bus.

Table 15—modified note 1, use L2CR[L2SL] for L2CLK frequency less than 150 MHz.

Table 8—revised note 2 discussing for 3.3-V bus voltage support.

Table 14—added note 5, do not use PL off during power-up sequence.

Table 1—update output hold times (tL2CHOX).

0.2

—

Corrected Section 1.3—technology from 0.13 µm to 0.18 µm

Updated Table 7—adds power consumption numbers; adds note on estimated decrease w/o AltiVec.

Updated Table 8—adds minimum values for processor frequency and VCO frequency.

Updated Table 9—input setup, output valid times, output hold times, SYSCLK to output high

impedance.

Updated Table 11—L2SYNC_IN to high impedance.

Updated Figure 17—mechanical dimensions, adds capacitor pad dimensions.

0.1

—

Minor updates.

—

Initial release.

Table 16. Document Revision History (continued)

Revision

Date

Substantive Change(s)

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