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VSC8540XMVRT-HC データシート(PDF) 45 Page - Microchip Technology

部品番号 VSC8540XMVRT-HC
部品情報  Radiation-Tolerant Single Port Fast Ethernet Copper PHY with RGMII/MII/RMII Interfaces
PDF  87 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

VSC8540XMVRT-HC データシート(HTML) 45 Page - Microchip Technology

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2022 Microchip Technology Inc. and its subsidiaries
DS60001603E-page 45
VSC8540RT
Note:
When bits 5:4 are set to jumbo packet mode, the default maximum packet values are based on 100 ppm
driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY as specified
in the bit description results in a higher jumbo packet length.
6.2.19
INTERRUPT MASK
These bits control the device interrupt mask. The following table shows the settings available.
Note:
When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the state of
bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted. Also, before enabling this bit,
read register 26 to clear any previously inactive interrupts pending that will cause bit 25.15 to be set.
12
PICMG 2.16 reduced power mode R/W
Sticky bit.
1: Enabled.
0
11:6
Reserved
RO
Reserved.
5:4
Jumbo packet mode
R/W
Sticky bit.
00: Normal IEEE 1.5 kB packet length.
01: 9 kB jumbo packet length (12 kB with
60 ppm or better reference clock).
10: 12 kB jumbo packet length (16 kB with
70 ppm or better reference clock).
11: Reserved.
00
3:1
Reserved
RO
Reserved.
0
Connector loopback
R/W
1: Enabled.
0
TABLE 6-22:
INTERRUPT MASK, ADDRESS 25 (0X19)
Bit
Name
Access
Description
Default
15
MDINT interrupt status enable
R/W
Sticky bit. 1: Enabled.
0
14
Speed state change mask
R/W
Sticky bit. 1: Enabled.
0
13
Link state change mask
R/W
Sticky bit. 1: Enabled.
0
12
FDX state change mask
R/W
Sticky bit. 1: Enabled.
0
11
Autonegotiation error mask
R/W
Sticky bit. 1: Enabled.
0
10
Autonegotiation complete mask
R/W
Sticky bit. 1: Enabled.
0
9
Inline-powered device (PoE) detect mask R/W
Sticky bit. 1: Enabled.
0
8
Symbol error interrupt mask
R/W
Sticky bit. 1: Enabled.
0
7
Fast link failure interrupt mask
R/W
Sticky bit. 1: Enabled.
0
6
Wake-on-LAN event interrupt mask
R/W
Sticky bit. 1: Enabled.
0
5
Extended interrupt mask
R/W
Sticky bit. 1: Enabled.
0
4
Reserved
RO
Reserved.
3
False carrier interrupt mask
R/W
Sticky bit. 1: Enabled.
0
2
Reserved
RO
Reserved.
1
Reserved
RO
Reserved.
0
RX_ER interrupt mask
R/W
Sticky bit. 1: Enabled.
0
TABLE 6-21:
EXTENDED PHY CONTROL 2, ADDRESS 24 (0X18) (CONTINUED)
Bit
Name
Access
Description
Default



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