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VSC8540XMVRT-HC データシート(PDF) 47 Page - Microchip Technology |
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VSC8540XMVRT-HC データシート(HTML) 47 Page - Microchip Technology |
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47 / 87 page ![]() 2022 Microchip Technology Inc. and its subsidiaries DS60001603E-page 47 VSC8540RT 6.2.22 LED MODE SELECT The device LED outputs are controlled using the bits in register 29 of the main register space. The following table shows the information needed to access the functionality of each of the outputs. For more information about LED modes, see Table 5-14. For information about enabling the extended LED mode bits in Register 19E1 bits 13 to 12, see Table 5-16 . 6.2.23 LED BEHAVIOR The bits in register 30 control and enable you to read the status of the pulse or blink rate of the device LEDs. The fol- lowing table shows the settings you can write to the register or read from the register. 7 ActiPHY link status time-out control [1] R/W Sticky bit. Bits 7 and 2 are part of the ActiPHY Link Status time-out control. Bit 7 is the MSB. 00: 2.3 seconds. 01: 3.3 seconds. 10: 4.3 seconds. 11: 5.3 seconds. 0 6 ActiPHY mode enable R/W Sticky bit. 1: Enabled. 0 5 FDX status RO 1: Full-duplex. 0: Half-duplex. 0 4:3 Speed status RO 00: Speed is 10BASE-T. 01: Speed is 100BASE-TX. 10: Reserved. 11: Reserved. 00 2 ActiPHY link status time-out control [0] R/W Sticky bit. Bits 7 and 2 are part of the ActiPHY Link Status time-out control. Bit 7 is the MSB. 00: 2.3 seconds. 01: 3.3 seconds. 10: 4.3 seconds. 11: 5.3 seconds. 1 1:0 Media mode status RO 00: No media selected. 01: Copper media selected. 10: Reserved. 11: Reserved. 00 TABLE 6-25: LED MODE SELECT, ADDRESS 29 (0X1D) Bit Name Access Description Default 15 Reserved RO Reserved. 14:8 Reserved RO Reserved. 7:4 LED1 mode select R/W Sticky bit. Select from LED modes 0–15. 0101 3:0 LED0 mode select R/W Sticky bit. Select from LED modes 0–15. 0100 TABLE 6-26: LED BEHAVIOR, ADDRESS 30 (0X1E) Bit Name Access Description Default 15:13 Reserved RO Reserved. 12 LED pulsing enable R/W Sticky bit. 0: Normal operation. 1: LEDs pulse with a 5 kHz, programmable duty cycle when active. 0 TABLE 6-24: AUXILIARY CONTROL AND STATUS, ADDRESS 28 (0X1C) (CONTINUED) Bit Name Access Description Default |
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