L9966 datasheet(39/122 Pages) STMICROELECTRONICS

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Figure 18. ADC conversion chain

GADG0801181056PS

In order to start the sequencer correctly, INIT_PC_EUx[3:0] field in SQNCR_CTRL register has to be properly

filled, for both EUx, with the first sequence lines. By default, in fact, INIT_PC_EUx[3:0] points to the ENDLOOP.

The sequencer is blocked if it starts (through SYNC signal if EUx_SYNC_EN =1 or SPI if EUx_EN=1) with

INIT_PC_EUx[3:0] = ENDLOOP.

Once the sequencer runs (EUx_EN=1) any write access to SQNCR_CTRL register is ignored, avoiding any

unpredictable operation sequence.

In case the sequencer is running, any modification in its configuration requires the sequencer to be stopped

resetting EUx_SYNC_EN and EUx_EN in SQNCR_CTRL register.

9.2.1

Sequencer channels addressing

The sequencer can use both the ADC1 for voltage measurements and ADC2 for resistance measurements.

Each input channel measurement is configurable through a dedicated register SQNCR_CMD_x [x=1:15] . The

measurement results are instead readable in the register SQNCR_RESULT_x [x=1:15]. Table 24 shows the

addresses for configuration and result lines.

For ADC1, the meaningful input channels are:

•

all the analog channels IO[12:1]

•

UBSW, VI5V and VIX pins.

For ADC2, the meaningful input channels are:

•

all the analog channels IO[12:1]

UBSW, VI5V and VIX pins can be fed into ADC2, but the results are meaningless.

L9966

Sequencer

DS12459 - Rev 10

page 39/122

L9966 データシート(PDF) 39 Page - STMicroelectronics