L99DZ100GP datasheet(84/197 Pages) STMICROELECTRONICS

84 / 197 page

Application information

L99DZ100G, L99DZ100GP

84/197

DS11546 Rev 5

4.8

Reset output (NReset)

Figure 27. NReset pin

If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output NReset is

pulled up to V1 by an internal pull-up resistor after a reset delay time (tV1R). This is

necessary for a defined start of the micro controller when the application is switched on.

Since the NReset output is realized as an open drain output it is also possible to connect an

external NReset open drain NReset source to the output. As soon as the NReset is released

by the devices the watchdog starts with a long open window.

A reset pulse is generated in case of:



V1 drops below VRTxfalling (configurable by SPI) for t > tUV1



Watchdog failure



Turn-on of the V1 regulator (VSREG Power-on or wake-up from Vbat_standby mode)

Table 65. Non-recoverable failure

Failure source

Failure condition

Diagnosis

Exit from Fail-safe mode

Microcontroller

(Oscillator)

15 consecutive

Watchdog Failures

FS (Global Status Byte) = 1; WDFAIL (SR

1) = 1; FORCED_SLEEP_WD (SR 1) = 1

Wake-up;

TRIG (CR 1) = 1 during long

open window; Read&Clear

SR1

Short at turn-on

FS (Global Status Byte) = 1;

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

Wake-up;



Read&Clear SR1

Temperature

7 times TSD2

FS (Global Status Byte) =1; TW (SR 2) = 1;

TSD1 (SR 1) = 1; TSD2 (SR 1) = 1;

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

Wake-up;



Read&Clear SR1

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