L99DZ100GP datasheet(91/197 Pages) STMICROELECTRONICS

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DS11546 Rev 5

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L99DZ100G, L99DZ100GP

Application information

196

transceiver is in a low power mode (TRX_BIAS or TRX_Sleep) the device can be woken up

by sending 2 consecutive dominant bits separated by a recessive bit.

A wake-up can be detected if the CAN transceiver was set in standby mode while the CAN

bus was in recessive (high) state or dominant (low) state (see Figure 32: CAN wake up

capabilities).

Figure 32. CAN wake up capabilities

For details, see Figure 31: CAN transceiver state diagram

Wakeup by Wake-up Frame (WUF)

In this configuration, the wake-up behavior is according to ISO 11898-6:2013. This option is

activated by setting SWEN = 1. Upon reception of a valid wake up frame, an interrupt will be

generated, the WUF flag will be set and the device enters Active mode.

The included frame-error-counter according ISO 11898-6:2013 is reset whenever selective

wake-up is set to enable and whenever tSilence has expired in TRX BIAS state (i.e. either on

a transition SWEN = 0 -> 1 or on a transition TRX BIAS -> TRX Sleep).

To detect a failure of the internal 32 MHz oscillator, the following mechanism is

implemented. While selective wake-up is enabled a timer is started with each recessive to

dominant edge. After 64 µs and with periodic 64 µs timer, a check is performed on CAN PN

oscillator activity, and if an oscillator fail is detected, the osc_mon bit is set to ‘1’.

Subsequently the device enters wake-up mode according to ISO11898-5 (wake-up pattern

wake-up).

For details, see Figure 31: CAN transceiver state diagram.

Sequence for enabling selective wakeup

After Power-On-Reset, the selective wakeup feature is disabled. The PN Configuration

Registers have to be read and verified by the microcontroller in order to ensure a valid

configuration. A read operation to Registers CR23 to CR29 is required to allow enabling the

selective wake-up feature (set SWEN=1). SWRD_CRxx (SR 12) bits will indicate a valid

read operation. The SWRD_CRxx bits are reset to 0 with every WRITE operation.

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