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L99DZ100GP データシート(PDF) 18 Page - STMicroelectronics |
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L99DZ100GP データシート(HTML) 18 Page - STMicroelectronics |
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18 / 197 page ![]() Block diagram and pin descriptions L99DZ100G, L99DZ100GP 18/197 DS11546 Rev 5 47 PWMH PWMH input: this input signal can be used to control the H-bridge Gate Drivers. 48 DIRH Direction Input: this input controls the H-bridge Drivers for the external MOSFETs 49 DIR2 Direct Drive Input 2 50 NRESET NReset output to micro controller; (reset state = LOW) (Low-side switch with drain connected to the output pin and internal pull up resistance to 5V_1) 51 5V_1 Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN transceiver 52 CAN Supply CAN supply input; to allow external CAN supply from V1 or V2 regulator 53 NINT Interrupt output (low active; push-pull output stage) to indicate VSREG early warning (Active mode); indicates wake-up events from V1_standby mode 54 CAN_L CAN low level voltage I/O 55 CAN_H CAN high level voltage I/O 56 Debug Debug input to deactivate the window watchdog (high active) 57 LIN LIN bus line 58 5V_2 Voltage regulator 2 output: 5 V supply for external loads (potentiometer, sensors) or CAN Transceiver. V2 is protected against reverse supply 59 GL1 Gate driver for PowerMOS low-side switch in half-bridge 1 60 SH1 Source of high-side switch in half-bridge 1 61 GH1 Gate driver for PowerMOS high-side switch in half-bridge 1 62 GH2 Gate driver for PowerMOS high-side switch in half-bridge 2 63 SH2 Source of high-side switch in half-bridge 2 64 GL2 Gate driver for PowerMOS low-side switch in half-bridge 2 Table 2. Pin definitions and functions (continued) Pin Symbol Function |
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