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C5C5EDELTA-RM/D データシート(PDF) 53 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D データシート(HTML) 53 Page - NXP Semiconductors |
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53 / 114 page  Pin Descriptions Grouped by Function 53 03 TLU SRAM Interface Signals The TLU SRAM interface supports up to 128MBytes of SRAM at frequencies to 125MHz using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to 64Mbits. The TLU SRAM interface signals are described in Table 23. Table 23 TLU SRAM Interface Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION TD0 - TD63 F3, F4, F5, F6, F7, F8, G1, G3, G4, G5, G7, G8, H1, H2, H3, H5, H6, H7, H8, J1, J2, J3, J5, J6, J7, J8, K1, K3, K4, K5, K7, K8, L1, L2, L3, L4, L5, L6, L7, L8, M1, M2, M3, M5, M6, M7, M8, N1, N2, N3, N4, N5, N6, N7, N8, P1, P3, P4, P5, P7, P8, R1, R2, R3 64 LVTTL I PD/O TLU Memory Data TA0 - TA21 U2, U3, U4, U5, U6, U7, U8, V1, V3, V4, V5, V7, V8, W1, W2, W3, W5, W6, W7, W8, Y1, Y2 22 LVTTL O PD TLU Memory Address TPAR0 - TPAR3 T1, T2, T3, T5 4 LVTTL I PD/O Word Data Parity (i.e. TPAR0 across TD15:0) TCE0X - TCE3X T6, T7, T8, U1 4 LVTTL O PD TLU Memory Chip Enable TWE0X - TWE3X R5, R6, R7, R8 4 LVTTL O PD TLU Memory Write Enable TCLKI R4 1 LVTTL I PD TLU Clock Input TOTAL PINS 99 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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