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C5C5EDELTA-RM/D データシート(PDF) 81 Page - NXP Semiconductors

部品番号 C5C5EDELTA-RM/D
部品情報  C-3e Network Processor Silicon Revision A1
PDF  114 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

C5C5EDELTA-RM/D データシート(HTML) 81 Page - NXP Semiconductors

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AC Timing Specifications
81
03
CP Timing Specifications
This section describes the timing for the following CP interfaces:
• DS1/DS3
• 10/100 Ethernet
• Gigabit Ethernet
• OC-3
• OC-12
DS1/DS3 Timing Specifications
The DS1/DS3 interface timing is shown in Figure 14 and described in Table 38.
Figure 14 DS1/DS3 Ethernet Timing Diagram
CPn_0 (TCLK)
Cycle 1
Cycle 2
Cycle 2
Cycle 3
Cycle 3
Cycle 4
Cycle 4
Cycle 5
Cycle 5
CPn_2/3 (Tx)
CPn_1 (RCLK)
CPn_4/5 (Rx)
Tcdt
Tcdo
Tcdr
Tcds
Tcdh
Table 38 DS1/DS3 Ethernet Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tcdt
DS1/DS3 Transmit Cycle Time
647/22.4
ns
Tcdo
DS1/DS3 Output Time
3.0/3.0
400/15.0
ns
Tcdr
DS1/DS3 Receive Cycle Time
647/22.4
ns
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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