STM32U535NET6QTR datasheet(69/278 Pages) STMICROELECTRONICS

69 / 278 page

DS14217 Rev 1

69/278

STM32U535xx

Functional overview

3.35

HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm

(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and

the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for

applications requiring message authentication.

The HASH computes FIPS (Federal information processing standards) approved digests of

length of 160, 224, 256 bits, for messages of up to (264 – 1) bits. It also computes 128 bits

digests for the MD5 algorithm.

The HASH main features are:

•

Suitable for data authentication applications, compliant with:

–

Federal Information Processing Standards Publication FIPS PUB 180-4, Secure

Hash Standard (SHA-1 and SHA-2 family)

–

Federal Information Processing Standards Publication FIPS PUB 186-4, Digital

Signature Standard (DSS)

–

Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5

Message-Digest Algorithm

–

Internet Engineering Task Force (IETF) Request For Comments RFC 2104,

HMAC: Keyed-Hashing for Message Authentication and Federal Information

Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message

Authentication Code (HMAC)

•

Fast computation of SHA-1, SHA-224, SHA-256, and MD5

–

82 (respectively 66) clock cycles for processing one 512-bit block of data using

SHA-1 (respectively SHA-256) algorithm

–

66 clock cycles for processing one 512-bit block of data using MD5 algorithm

•

Corresponding 32-bit words of the digest from consecutive message blocks are added

to each other to form the digest of the whole message:

–

Automatic 32-bit words swapping to comply with the internal little-endian

representation of the input bit string

–

Word swapping supported: bits, bytes, half-words and 32-bit words

•

Automatic padding to complete the input bit string to fit digest minimum block size of

512 bits (16 × 32 bits)

•

Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,

corresponding to one block size

•

AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB

error is generated)

•

8 × 32-bit words (H0 to H7) for output message digest

•

Automatic data flow control with support of direct memory access (DMA) using one

channel. Single or fixed burst of 4 supported.

•

Interruptible message digest computation, on a per-32-bit word basis

–

Re-loadable digest registers

–

Hashing computation suspend/resume mechanism, including using DMA

STM32U535NET6QTR データシート(PDF) 69 Page - STMicroelectronics

STM32U535NET6QTR データシート(HTML) 69 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード