AD9380SLASHPCB datasheet(44/60 Pages) AD

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AD9380

Rev. 0 | Page 44 of 60

0x27—Bit[7] Auto Power-Down Enable

This bit enables the chip to go into low power mode, or seek

mode if no sync inputs are detected. 0 = auto power-down

disabled. 1 = chip powers down if no sync inputs present. The

power-up default setting is 1.

0x27—Bit[6] HDCP A0 Address

This bit sets the LSB of the address of the HDCP I2C. This

should be set to 1 only for a second receiver in a dual-link

configuration. The power-up default is 0.

0x27—Bits[5] MCLK External Enable

This bit enables the MCLK to be supplied externally. If an

external MCLK is used, then it must be locked to the video

clock according to the CTS and N available in the I2C. Any

mismatch between the internal MCLK and the input MCLK

results in dropped or repeated audio samples. 0 = use internally

generated MCLK. 1 = use external MCLK input. The power-up

default setting is 0.

BT656 GENERATION

0x27—Bit[4] BT656 Enable

This bit enables the output to be BT656 compatible with the

defined start of active video (SAV) and the end of active video

(EAV) controls to be inserted. These require specification of the

number of active lines, active pixels per line, and delays to place

these markers. 0 = disable BT656 video mode. 1 = enable BT656

video mode. The power-up default setting is 0.

0x27—Bit[3] Force DE Generation

This bit allows the use of the internal DE generator in DVI

mode. 0 = internal DE generation disabled. 1 = force DE

generation via programmed registers. The power-up default

setting is 0.

0x27—Bits[2:0] Interlace Offset

These bits define the offset in HSYNCs from Field 0 to Field 1.

The power-up default setting is 000.

0x28—Bits[7:2] VSYNC Delay

These bits set the delay (in lines) from the leading edge of

VSYNC to active video. The power-up default setting is 24.

0x28—Bits[1:0] HSYNC Delay MSBs

These 8 bits and the following 10 bits set the delay (in pixels)

from the HSYNC leading edge to the start of active video. The

power-up default setting is 0x104.

0x29—Bits[7:0] HSYNC Delay LSBs

See the HSYNC Delay MSBs section.

0x2A—Bits[3:0] Line Width MSBs

These 8 bits and the following 12 bits set the width of the active

video line (in pixels). The power-up default setting is 0x500.

0x2B—Bits[7:0] Line Width LSBs

See the line width MSBs section.

0x2C—Bits[3:0] Screen Height MSBs

Along with the 8 bits following these 12 bits, set the height of

the active screen (in lines). The power-up default setting is

0x2D0.

0x2D—Bits[7:0] Screen Height LSBs

See the Screen Height MSBs section.

0x2E—Bit[7] Ctrl Enable

When set, this bit allows Ctrl [3:0] signals decoded from the

DVI to be output on the I2S data pins. 0 = I2S signals on I2S

lines. 1 = Ctrl [3:0] output on I2S lines. The power-up default

setting is 0.

0x2E—Bits[6:5] I2S Output Mode

These bits select between four options for the I2S output: I2S,

right-justified, left-justified, or raw IEC60958 mode. The

power-up default setting is 00.

Table 21. I2S Output Select

I2S Output Mode

Result

I2S mode

Right-justified

Left-justified

Raw IEC60958 mode

0x2E—Bits[4:0] I2S Bit Width

These bits set the I2S bit width for right-justified mode. The

power-up default setting is 24 bits.

0x2F—Bit[6] TMDS Sync Detect

This read-only bit indicates the presence of a TMDS DE. 0 = no

TMDS DE present. 1 = TMDS DE detected.

0x2F—Bit[5] TMDS Active

This read-only bit indicates the presence of a TMDS clock. 0 =

no TMDS clock present. 1 = TMDS clock detected.

0x2F—Bit[4] AV Mute

This read-only bit indicates the presence of AV mute based on

general control packets. 0 = AV not muted. 1 = AV muted.

0x2F—Bit[3] HDCP Keys Read

This read-only bit reports if the HDCP keys were read

successfully. 0 = failure to read HDCP keys. 1 = HDCP keys

read.

0x2F—Bit[2:0] HDMI Quality

These read-only bits indicate a level of HDMI quality based on

the display enable (DE) edges. The 3 bits correspond to the R,

G, and B channels of the TMDS signals. If an extraneous signal

is present on any channel, that bit is set. A value of 000

represents the highest quality.

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