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AD9380/PCB データシート(PDF) 23 Page - Analog Devices |
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AD9380/PCB データシート(HTML) 23 Page - Analog Devices |
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23 / 60 page  AD9380 Rev. 0 | Page 23 of 60 2-WIRE SERIAL REGISTER MAP The AD9380 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 12. Control Register Map Hex Address Read/Write or Read-Only Bits Default Value Register Name Description 0x00 Read [7:0] 00000000 Chip Revision Chip revision ID. 0x01 Read/Write [7:0] 01101001 PLL Divider MSB PLL feedback divider value MSB. 0x02 Read/Write [7:4] 1101**** PLL Divider PLL feedback divider value. 0x03 Read/Write [7:6] 01****** VCO Range VCO range. [5:3] **001*** Charge Pump Charge pump current control for PLL. [2] *****0** External Clock Enable Selects the external clock input rather than the internal PLL clock. 0x04 Read/Write [7:3] 10000*** Phase Adjust Selects the clock phase to use for the ADC clock. 0x05 Read/Write [7:0] 10000000 Red Gain Controls the gain of the red channel PGA. 0 = low gain, 255 = high gain. 0x06 Read/Write [7:0] 10000000 Green Gain Controls the gain of the green channel PGA. 0 = low gain, 255 = high gain. 0x07 Read/Write [7:0] 10000000 Blue Gain Controls the gain of the blue channel PGA. 0 = low gain, 255 = high gain. 0x08 Read/Write [7:0] 00000000 Red Offset Adjust User adjustment of auto-offset. Allows user control of brightness. 0x09 Read/Write [7:0] 10000000 Red Offset Red offset/target code. 0 = small offset, 255 = large offset. 0x0A Read/Write [7:0] 00000000 Green Offset Adjust User adjustment of auto-offset. Allows user control of brightness. 0x0B Read/Write [7:0] 10000000 Green Offset Green offset/target code. 0 = small offset, 255 = large offset. 0x0C Read/Write [7:0] 00000000 Blue Offset Adjust User adjustment of auto-offset. Allows user control of brightness. 0x0D Read/Write [7:0] 10000000 Blue Offset Blue offset/target code. 0 = small offset, 255 = large offset. 0x0E Read/Write [7:0] 00100000 Sync Separator Threshold Selects the maximum HSYNC pulse width for composite sync separation. 0x0F Read/Write [7:2] 010000** SOG Comparator Threshold Enter The enter level for the SOG slicer. Must be less than or equal to the exit level. 0x10 Read/Write [7:2] 010000** SOG Comparator Threshold Exit The exit level for the SOG slicer. Must be greater than or equal to the enter level. 0x11 Read/Write [7] 0******* HSYNC Source 0 = HSYNC. 1 = SOG. [6] *0****** HSYNC Source Override 0 = auto HSYNC source. 1 = manual HSYNC source. [5] **0***** VSYNC Source 0 = VSYNC. 1 = VSYNC from SOG. [4] ***0**** VSYNC Source Override 0 = auto HSYNC source. 1 = manual HSYNC source. [3] ****0*** Channel Select 0 = Channel 0. 1 = Channel 1. [2] *****0** Channel Select Override 0 = autochannel select. 1 = manual channel select. [1] ******0* Interface Select 0 = analog interface. 1 = digital interface. [0] *******0 Interface Override 0 = auto-interface select. 1 = manual interface select. |
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