SST25WF080B datasheet(16/44 Pages) MICROCHIP

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SST25WF080B

DS20005164H-page 16

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5.8

Chip Erase

The Chip Erase instruction clears all bits in the device

to FFH. A Chip Erase instruction is ignored if any of the

memory area is protected. Prior to any write operation, the

Write Enable (WREN) instruction must be executed. CE#

must remain active-low for the duration of the Chip

Erase instruction sequence. Initiate the Chip Erase

instruction by executing an 8-bit command, 60H or

C7H. CE# must be driven high before the instruction is exe-

cuted. Poll the BUSY bit in the Software STATUS regis-

ter, or wait TSCE, for the completion of the internal self-

timed Chip Erase cycle. See Figure 5-8 for the Chip

Erase sequence and Figure 6-10 for the flow chart.

FIGURE 5-8:

CHIP ERASE SEQUENCE

5.9

Read STATUS Register (RDSR)

The Read STATUS Register (RDSR) instruction, 05H,

allows reading of the STATUS register. The STATUS

(program/erase) operation. When a write operation is in

progress, the BUSY bit may be checked before send-

ing any new commands to assure that the new com-

mands are properly received by the device. CE# must

be driven low before the RDSR instruction is entered

and remain low until the status data is read. Read STA-

TUS Register is continuous with ongoing clock cycles

until it is terminated by a low-to-high transition of the

CE#. See Figure 5-9 for the RDSR instruction

sequence.

FIGURE 5-9:

READ STATUS REGISTER (RDSR) SEQUENCE

CE#

SCK

0 1 234 5 6 7

60 or C7

High-Impedance

MODE 0

MODE 3

MSb

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

High-Impedance

STATUS

MSb

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