Data Sheet

AD9913

Rev. E | Page 31 of 32

Linear Sweep Parameter Register

Address 0x06, 8 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary

Accumulator section.

Table 15. Bit Descriptions for Linear Sweep Limit Register

Bit(s)

Bit Name

Description

63:32

Sweep Parameter Word 1

32-bit linear sweep upper limit value. In programmable modulus mode, these bits are used

to set the B value found in the AN-953 Application Note.

31:0

Sweep Parameter Word 0

32-bit linear sweep lower limit value. In programmable modulus mode, these bits are used

to set the X value found in the AN-953 Application Note.

Linear Sweep Delta Parameter Register

Address 0x07, 8 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary

Accumulator section.

Table 16. Bit Descriptions for Linear Sweep Step Size Register

Bit(s)

Bit Name

Description

63:32

Falling Delta Word

32-bit linear sweep decrement step size value.

31:0

Rising Delta Word

32-bit linear sweep increment step size value. In programmable modulus mode, these bits

are used to set the A value found in the AN-953 Application Note.

Linear Sweep Ramp Rate Register

Address 0x08, 4 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary

Accumulator section.

Table 17. Bit Descriptions for Linear Sweep Rate Register

Bit(s)

Bit Name

Description

31:16

Falling Sweep Ramp Rate

16-bit linear sweep negative slope value that defines the time interval between decrement

values.

15:0

Rising Sweep Ramp Rate

16-bit linear sweep positive slope value that defines the time interval between increment

values.

Profile Registers

There are eight consecutive serial I/O addresses dedicated to device profiles. In normal operation, the active profile register is selected

using the external profile select pins.

Profile 0 to Profile 7—Single Tone Register

Address 0x09 to Address 0x10, 6 bytes are assigned to these registers.

Table 18. Bit Descriptions for Profile 0 to Profile 7 Single Tone Register

Bit(s)

Bit Name

Description

47:46

Open

Leave these bits at their default state.

45:32

Phase Offset Word

This 14-bit number controls the DDS phase offset.

31:0

Frequency Tuning Word

This 32-bit number controls the DDS frequency.