AD9913SLASHPCBZ datasheet(15/32 Pages) AD

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Data Sheet

AD9913

Rev. E | Page 15 of 32

Table 5. Determining the Direction of the Linear Sweep

Profile Pins [2:0] or CFR1 Bits [22:20]

Linear Sweep Mode

x001

Sweep off

x011

Ramp up

x101

Ramp down

x111

Bidirectional ramp

1 x = don’t care.

Note that if the part is used in parallel port programming

mode, the sweep mode is only determined by the internal

profile control bits, CFR1 [22:20]. If the part is used in serial

port programming mode, either the internal profile control bits

or the external profile select pins can work as the sweep control.

CFR1 [27] selects between these two approaches.

Setting the Slope of the Linear Sweep

The slope of the linear sweep is set by the intermediate step size

(delta tuning word) between S0 and E0 (see Figure 22) and the

time spent (sweep ramp rate word) at each step. The resolution

of the delta tuning word is 32 bits for frequency and 14 bits for

phase. The resolution for the delta ramp rate word is 16 bits.

In linear sweep mode, the user programs a rising delta word

(RDW, Register 0x07) and a rising sweep ramp rate (RSRR,

E0. The falling delta word (FDW, Register 0x07) and falling

sweep ramp rate (FSRR, Register 0x08) apply when sweeping

from E0 to S0.

Note that if the auxiliary accumulator is allowed to overflow, an

uncontrolled, continuous sweep operation occurs. To avoid

this, the magnitude of the rising or falling delta word should be

smaller than the difference between full-scale and the E0 value

(full-scale − E0). For a frequency sweep, full-scale is 232 − 1. For

a phase sweep, full-scale is 214 − 1.

Figure 22 displays a linear sweep up and then down. This

depicts the dwell mode (see CRF1 [8]). If the no-dwell bit,

CFR1 [8], is set, the sweep accumulator returns to 0 upon

reaching E0.

TIME

RDW

FDW

RSRR

FSRR

Δf, p

Δt

Figure 22. Linear Sweep Mode

For a piecemeal or a nonlinear transition between S0 and E0,

the delta tuning words and ramp rate words can be reprogram-

med during the transition.

The formulas for calculating the step size of RDW or FDW are

SYSCLK

RDW

Step

Frequency















(MHz)











 



RDW

Step

Phase

(radians)















45RDW

Step

Phase

(degrees)

The formula for calculating delta time from RSRR or FSRR is





(Hz)

SYSCLK

RSRR

t 



At 250 MSPS operation, (fSYSCLK =250 MHz). The minimum time

interval between steps is 1/250 MHz × 1 = 4 ns. The maximum

time interval is (1/250 MHz) × 65,535= 262 μs.

Frequency Linear Sweep Example

In linear sweep mode, when sweeping from low to high, the

RDW is applied to the input of the auxiliary accumulator and

the RSRR register is loaded into the sweep rate timer.

The RDW accumulates at the rate given by the ramp rate

(RSRR) until the output equals the upper limit in the linear

sweep parameter register (Register 0x06). The sweep is then

complete.

When sweeping from high to low, the FDW is applied to the

input of the auxiliary accumulator and the FSRR register is

loaded into the sweep rate timer.

The FDW accumulates at the rate given by the ramp rate

(FSRR) until the output equals the lower limit in the linear

sweep parameter register value (Register 0x06). The sweep is

then complete. A phase sweep works in the same manner with

fewer bits.

To view sweep capabilities using the profile pins and the no-

dwell bit, refer to Figure 23, Figure 24, and Figure 25.

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