ICS9FG104 datasheet(4/17 Pages) IDT

4 / 17 page

IDTTM/ICSTM

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

ICS9FG104

REV K 04/12/07

ICS9FG104

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

General SMBus serial interface information for the ICS9FG104

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address DC

(H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

(see Note 2)

• ICS clock will

acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address DC

(H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address DD

(H)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8).

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Sla ve /Re ce ive r)

ACK

PstoP bit

Index Block Write Operation

Slave Address DC(H)

Beginning Byte = N

WRite

starT bit

Controlle r (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

starT bit

W Rite

Repeat starT

ReaD

Beginning Byte N

Byte N + X - 1

Not acknowledge

PstoP bit

ICS (S la ve /Re ce ive r)

Controlle r (Host)

ACK

Data Byte Count = X

ACK

Slave Address DD(H)

Index Block Read Operation

Slave Address DC(H)

Beginning Byte = N

ACK

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