Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

ICS9FG104

REV K 04/12/07

ICS9FG104

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

8

SMBus Table: PLL Frequency Control Register

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

PLL N Div7

RW

X

Bit 6

PLL N Div6

RW

X

Bit 5

PLL N Div5

RW

X

Bit 4

PLL N Div4

RW

X

Bit 3

PLL N Div3

RW

X

Bit 2

PLL N Div2

RW

X

Bit 1

PLL N Div1

RW

X

Bit 0

PLL N Div0

RW

X

SMBus Table: PLL Spread Spectrum Control Register

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

PLL SSP7

RW

X

Bit 6

PLL SSP6

RW

X

Bit 5

PLL SSP5

RW

X

Bit 4

PLL SSP4

RW

X

Bit 3

PLL SSP3

RW

X

Bit 2

PLL SSP2

RW

X

Bit 1

PLL SSP1

RW

X

Bit 0

PLL SSP0

RW

X

SMBus Table: PLL Spread Spectrum Control Register

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

0

Bit 6

PLL SSP14

RW

X

Bit 5

PLL SSP13

RW

X

Bit 4

PLL SSP12

RW

X

Bit 3

PLL SSP11

RW

X

Bit 2

PLL SSP10

RW

X

Bit 1

PLL SSP9

RW

X

Bit 0

PLL SSP8

RW

X

SMBus Table: Reserved Test Register

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

1

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

-

-

Reserved Test Register. Do not write to this register, erratic device operation may occur.

-

-

-

-

Byte 14

-

-

-

Spread Spectrum

Programming bit(14:8)

These Spread Spectrum bits in

Byte 13 and 14 will program the

spread pecentage of PLL

-

-

-

-

-

-

-

Byte 13

-Reserved

Byte 12

-

Spread Spectrum

Programming bit(7:0)

These Spread Spectrum bits in

Byte 13 and 14 will program the

spread pecentage of PLL

-

-

-

-

-

-

The decimal representation of M

and N Divider in Byte 11 and 12 will

configure the PLL VCO frequency.

Default at power up = latch-in or

Byte 0 Rom table. VCO Frequency

= 14.318 x [NDiv(9:0)+8] /

[MDiv(5:0)+2]

-

-

-

-

-

-

-

Byte 11

-

N Divider Programming

Byte11 bit(7:0) and Byte10

bit(7:6)