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ICS9FG104 データシート(PDF) 10 Page - Integrated Device Technology |
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ICS9FG104 データシート(HTML) 10 Page - Integrated Device Technology |
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10 / 17 page ![]() IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG104 REV K 04/12/07 ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 10 Absolute Max Electrical Characteristics - Input/Supply/Common Output Parameters Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage VDD + 0.5V V VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 VDD + 0.5V V Ts Storage Temperature -65 150 °C Tambient Ambient Operating Temp 0 70 °C Tcase Case Temperature 115 °C ESD prot Input ESD protection human body model 2000 V TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage VIH 3.3 V +/-5% 2 V DD + 0.3 V1 Input Low Voltage VIL 3.3 V +/-5% V SS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 IIL1 VIN = 0 V; Inputs with no pull- up resistors -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 Full Active, CL = Full load; f = 400 MHz 125 150 mA 1 Full Active, CL = Full load; f = 100 MHz 110 125 mA 1 All outputs stopped driven 106 120 mA 1 All outputs stopped Hi-Z 48 60 mA 1 Input Frequency 3 Fi VDD = 3.3 V 14 25 MHz 3 Pin Inductance 1 Lpin 7nH 1 CIN Logic Inputs 1.5 5 pF 1 COUT Output pin capacitance 6 pF 1 Clk Stabilization 1,2 TSTAB From VDD Power-Up and after input clock stabilization to 1st clock 1.8 ms 1,2 Modulation Frequency fMOD Triangular Modulation 30 33 kHz 1 DIF output enable tDIFOE DIF output enable after DIF_Stop# de-assertion 15 ns 1 Input Rise and Fall times tR/tF 20% to 80% of VDD 5 ns 1 1Guaranteed by design, not 100% tested in production. 2See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet Input/Output Capacitance 1 Input Low Current IDD3.3STOP IDD3.3OP Operating Supply Current |
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