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ICS9FG104 データシート(PDF) 7 Page - Integrated Device Technology

部品番号 ICS9FG104
部品情報  Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
PDF  17 Pages
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS9FG104 データシート(HTML) 7 Page - Integrated Device Technology

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IDTTM/ICSTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
REV K 04/12/07
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
7
SMBus Table: Reserved Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: Reserved Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: M/N Programming Enable
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
M/N_Enable
M/N Prog. Enable
RW
Disable
Enable
0
Bit 6
1
Bit 5
REFOUT_En
REFOUT Enable
RW
Disable
Enable
1
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
PLL N Div8
N Divider Prog bit 8
RW
X
Bit 6
PLL N Div9
N Divider Prog bit 9
RW
X
Bit 5
PLL M Div5
RW
X
Bit 4
PLL M Div4
RW
X
Bit 3
PLL M Div3
RW
X
Bit 2
PLL M Div2
RW
X
Bit 1
PLL M Div1
RW
X
Bit 0
PLL M Div0
RW
X
-
Byte 10
-
The decimal representation of M
and N Divider in Byte 11 and 12 will
configure the PLL VCO frequency.
Default at power up = latch-in or
Byte 0 Rom table. VCO Frequency
= 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
-
M Divider Programming
bit (5:0)
-
-
-
-
-Reserved
Reserved
Reserved
Reserved
-Reserved
-
-
-
5
-Reserved
Reserved
Byte 9
-
-
Reserved
Reserved
Reserved
Reserved
Byte 8
-
-
-
-
-
-
-
Byte 7
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved



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