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ICS9FG104 データシート(PDF) 11 Page - Integrated Device Technology |
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ICS9FG104 データシート(HTML) 11 Page - Integrated Device Technology |
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11 / 17 page  IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG104 REV K 04/12/07 ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 11 Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output Impedance Zo 1 VO = Vx 3000 Ω 1 Voltage High VHigh 660 850 1 Voltage Low VLow -150 150 1 Max VoltageVovs 1150 1 Min Voltage Vuds -300 1 Crossing Voltage (abs) Vcross(abs) 250 550 mV 1 Crossing Voltage (var) d-Vcross Crossing variation over all edges 140 mV 1 Long Accuracy ppmsee Tperiod min-max values -300 300 ppm 1,2,5 400MHz nominal 2.4993 2.5008 ns 2 400MHz spread 2.4993 2.5133 ns 2,3 333.33MHz nominal 2.9991 3.0009 ns 2 333.33MHz spread 2.9991 3.016 ns 2,3 266.66MHz nominal 3.7489 3.7511 ns 2 266.66MHz spread 3.7489 3.77 ns 2,3 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2,3 166.66MHz nominal 5.9982 6.0018 ns 2 166.66MHz spread 5.9982 6.0320 ns 2,3 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 5.4000 ns 2,3 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2,3 400MHz nominal/spread 2.4143 ns 1,2 333.33MHz nominal/spread 2.9141 ns 1,2 266.66MHz nominal/spread 3.6639 ns 1,2 200MHz nominal/spread 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.3728 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr 125 ps 1 Fall Time Variation d-tf 125 ps 1 Duty Cycle dt3 Measured Differentially 45 55 % 1 Skew, output to output tsk3 VT = 50% 35 ps 4 Jitter, PCI-e SRC phase tjPCI-ephase14 22MHz/1.5MHz/1.5MHz/10ns, 14.31818 MHz REF Clock 42 ps 4 Jitter, PCI-e SRC phase tjPCI-ephase25 22MHz/1.5MHz/1.5MHz/10ns, 25 MHz REF Clock 39 ps 4 Jitter, Cycle to cycle tjcyc-cyc Measured Differentially 50 ps 1 1Guaranteed by design and characterization, not 100% tested in production. 3 Figures are for down spread. 5 +/- 150 ppm for 100 MHz outputs 4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit http://www.pcisig.com for additional details 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz Statistical measurement on single ended signal using oscilloscope math function. mV Measurement on single ended signal using absolute value. mV Average period Tperiod Absolute min period Tabsmin |
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