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TMP92FD54AI データシート(PDF) 54 Page - Toshiba Semiconductor |
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TMP92FD54AI データシート(HTML) 54 Page - Toshiba Semiconductor |
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54 / 84 page  92FD54AI-54 2006-01-27 TMP92FD54AI (1) Block configuration Single-Chip Single Boot F80000H 010000H 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 56 Kbytes 56 Kbytes 8 Kbytes FFFFFFH 8 Kbytes 08FFFFH Figure 4.4.1 Flash memory block configuration (2) Flash memory interface during on-board programming Figure 4.4.2 is a conceptual diagram of the flash memory’s internal interface. Note, however, that this diagram is only a schematic representation of the interface between the CPU and flash memory, and does not represent the actual circuit. Figure 4.4.2 Flash memory internal interface Single-Chip Mode: F80000H to FFFFFFH Single-Boot Mode: 010000H to 08FFFFH Decoder Operation mode Flash memory DQ31 to DQ0 D31 to D0 A31 to A17 A16 to A2 AD14 to AD0 CPU CE WE OE WR RD RDY/BSY RESET CPU RESET (512 KB) Register |
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