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TMP92FD54AI データシート(PDF) 8 Page - Toshiba Semiconductor

部品番号 TMP92FD54AI
部品情報  CMOS 32-bit Micro-controller
PDF  84 Pages
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メーカー  TOSHIBA [Toshiba Semiconductor]
ホームページ  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP92FD54AI データシート(HTML) 8 Page - Toshiba Semiconductor

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2006-01-27
92FD54AI-8
TMP92FD54AI
Pin name
Pin
number
Number
of pins
In/Out
Function
PN1
SO0
SDA0
60th
1
in/out
out
in/out
Port N1: I/O port.
SBI channel 0: Output data input/output at SIO mode
SBI channel 0: Data input/output at I²C mode
PN2
SI0
SCL0
62nd
1
in/out
in
in/out
Port N2: I/O port.
SBI channel 0: Input data at SIO mode
SBI channel 0: Clock input/output at I²C mode
PN3
SCK1
A12
64th
1
in/out
in/out
out
Port N3: I/O port.
SBI channel 1: Clock input/output at SIO mode
Address: Address bus 12.
PN4
SO1
SDA1
A13
65th
1
in/out
out
in/out
out
Port N4: I/O port.
SBI channel 1: Output data at SIO mode
SBI channel 1: Data input/output at I²C mode
Address: Address bus 13.
PN5
SI1
SCL1
A14
66th
1
in/out
in
in/out
out
Port N5: I/O port.
SBI channel 1: Input data at SIO mode
SBI channel 1: Clock input/output at I²C mode
Address: Address bus 14
PN6
SO2
SDA2
A15
67th
1
in/out
out
Port N6: I/O port.
SBI channel 2: Output data at SIO mode
SBI channel 2: data input output at I2C mode
Address: Address bus 15.
NMI
39th
1
in
Non-maskable interrupt: Interrupt request pin with programmable falling or both
falling and rising edge.
INT0
37th
1
in
Interrupt request pin 0: Interrupt request pin with programmable level or
rising-edge.
Address mode pins: These pins are set as following,
AM0,1
80th, 78th
2
in
(Single-Chip mode)
(Single-Boot mode)
AM0 = L,
AM0 = H,
AM1 = H
AM1 = H
Test mode pins: These pins are set as following,
TEST0,1
76th, 71st
2
in
(Single Chip & Single Boot mode)
TEST0 = L, TEST1 = L
CLK
77th
1
out
Programmable clock output (with pull-up register).
X1/X2
74th, 72nd
2
in/out Oscillator connecting pins
XT1/XT2
70th, 69th
2
in/out Low frequency oscillator connecting pins. Crystal or ceramic resonator is connected.
RC oscillation is also possible depending on MASK option.
RESET
79th
1
in
Reset: Initializes LSI (with pull-up register).
VREFH
4th
1
in
AD reference voltage high
VREFL
3rd
1
in
AD reference voltage low
ADVCC
2nd
1
-
Power supply pin for AD converter (+5V): Connect ADVCC pin to 5V power supply.
ADVSS
1st
1
-
GND pin for AD converter: Connect ADVSS pin to GND (0V).
DVCC5
15th, 40th,
50th,61st,75th
5
-
Power supply pins (+5V): Connect all DVCC5 pins to 5V power supply.
DVCC3
36th,68th,86th
3
-
Power supply pins (+3.3V): Connect all DVCC3 pins to REGOUT pin.
DVSS
13th,38th,51st,
63rd,73rd,88th
6
-
GND: Connect all DVSS pins to GND (0V).
REGOUT
49th
1
out
Regulator output 3.3V: Connect capacitor to stabilize the regulator output.
REGEN
52nd
1
in
Regulator enable pin: Should be set to H or OPEN (with pull-up register).
INT0
NMI



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