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LAN9252/ML データシート(PDF) 250 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 250 Page - Microchip Technology |
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250 / 329 page  LAN9252 DS00001909A-page 250 2015 Microchip Technology Inc. Note 18: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu- rable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.31 ECAT EVENT MASK REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.32 AL EVENT MASK REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 0 I/O[1:0] Direction 0: Input 1: Output RO RO 0b Note 18 Offset: 0200h-0201h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 ECAT Event Mask ECAT event masking of the ECAT Event Request register Events for mapping into the ECAT event fields of EtherCAT frames. 0: Corresponding ECAT Event Request register bit is not mapped 1: Corresponding ECAT Event Request register bit is mapped R/W RO 0000h Offset: 0204h-0207h Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 AL Event Mask AL event masking of the AL Event Request register Events for mapping to the PDI IRQ signal. 0: Corresponding AL Event Request register bit is not mapped 1: Corresponding AL Event Request register bit is mapped RO R/W 00FFFF0Fh Bits Description ECAT Type PDI Type Default |
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