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LAN9252/ML データシート(PDF) 254 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 254 Page - Microchip Technology

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LAN9252
DS00001909A-page 254
 2015 Microchip Technology Inc.
12.14.35 RX ERROR COUNTER REGISTERS
There are 4 16-bit RX Error Counter registers, each with unique address offsets as shown above. The variable “x” is
used in the following bit descriptions to represent ports 0-3.
Note:
This register is cleared if any one of the RX Error Counter Registers is written.
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
Note:
Port 3 is not used.
Offset:
0300h-0307h
Port 0: 0300h-0301h
Port 1: 0302h-0303h
Port 2: 0304h-0305h
Port 3: 0306h-0307h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15:8
Port x RX Error Counter
Counting is stopped when FFh is reached. This is coupled
directly to RX ERR of the MII/EBUS interfaces.
R/WC
RO
00h
7:0
Port x Invalid Frame Counter
Counting is stopped when FFh is reached.
R/WC
RO



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