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LAN9252/ML データシート(PDF) 252 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 252 Page - Microchip Technology |
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252 / 329 page  LAN9252 DS00001909A-page 252 2015 Microchip Technology Inc. 12.14.34 AL EVENT REQUEST REGISTER Offset: 0220h-0223h Size: 32 bits Bits Description ECAT Type PDI Type Default 31:12 RESERVED RO RO 000h 11 SyncManager 3 Interrupts (SyncManager register offset 5h, bit 0 or 1) 0: No SyncManager 3 Interrupt 1: SyncManager 3 Interrupt pending RO RO 0b 10 SyncManager 2 Interrupts (SyncManager register offset 5h, bit 0 or 1) 0: No SyncManager 2 Interrupt 1: SyncManager 2 Interrupt pending RO RO 0b 9 SyncManager 1 Interrupts (SyncManager register offset 5h, bit 0 or 1) 0: No SyncManager 1 Interrupt 1: SyncManager 1 Interrupt RO RO 0b 8 SyncManager 0 Interrupts (SyncManager register offset 5h, bit 0 or 1) 0: No SyncManager 0 Interrupt 1: SyncManager 0 Interrupt pending RO RO 0b 7 RESERVED RO RO 0b 6 Watchdog Process Data 0: Has not expired 1: Has expired Note: This bit is cleared by reading the Watchdog Status Process Data Register. RO RO 0b 5 EEPROM Emulation 0: No command pending 1: EEPROM command pending Note: This bit is cleared by acknowledging the command in EEPROM Control/Status Register from PDI. RO RO 0b 4 SyncManager x Activation Register Changed (SyncManager x Activate Register) 0: No change in any SyncManager 1: At least one SyncManager changed Note: This bit is cleared by reading the corresponding Syn- cManager x Activate Register from PDI. RO RO 0b 3 State of DC SYNC1 (If Sync/Latch PDI Configuration Register bit 7 = 1) Note: Bit is cleared by reading SYNC1 status 0x098F. RO RO 0b 2 State of DC SYNC0 (If Sync/Latch PDI Configuration Register bit 3 = 1) Note: Bit is cleared by reading SYNC0 status 0x098E. RO RO 0b |
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