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LAN9252/ML データシート(PDF) 253 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 253 Page - Microchip Technology |
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253 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 253 LAN9252 Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 1 DC Latch Event 0: No change on DC Latch Inputs 1: At least one change on DC Latch Inputs Note: This bit is cleared by reading the DC Latch event times from PDI for PDI controlled Latch Units, so that the LATCH0 Status Register/LATCH1 Status Register indicates no event. RO RO 0b 0 AL Control Event 0: No AL Control Register change 1: AL Control Register has been written (AL control event is only generated if PDI emulation is turned off (ESC Configuration Register bit 8 = 0). Note: This bit is cleared by reading the AL Control Register from PDI. RO RO 0b Bits Description ECAT Type PDI Type Default |
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