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LAN9252/ML データシート(PDF) 257 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 257 Page - Microchip Technology |
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257 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 257 LAN9252 12.14.40 LOST LINK COUNTER REGISTERS There are 4 8-bit Lost Link Counter registers, each with unique address offsets as shown above. The variable “x” is used in the following bit descriptions to represent ports 0-3. Note: This register is cleared if any one of the Lost Link Counter Registers is written. Note: Port 3 is not used. 12.14.41 WATCHDOG DIVIDER REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0310h-0313h Port 0: 0310h Port 1: 0311h Port 2: 0312h Port 3: 0313h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:0 Port x Lost Link Counter Counting is stopped when FFh is reached. This counter only counts if port loop is Auto or Auto-Close. Note: Only lost links at open ports are counted. R/WC RO 00h Offset: 0400h-0401h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Watchdog Divider Number of 25MHz ticks (minus 2) that represents the basic watchdog increment. (default value is 100 us = 2498) R/W RO 09C2h |
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