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LAN9252/ML データシート(PDF) 261 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 261 Page - Microchip Technology |
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261 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 261 LAN9252 12.14.48 EEPROM PDI ACCESS STATE REGISTER Note 19: Write access only possible if the PDI EEPROM Control bit of the EEPROM Configuration Register is 1 and Force ECAT Access bit is 0. Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. 12.14.49 EEPROM CONTROL/STATUS REGISTER Offset: 0501h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:1 RESERVED Write 0. RO RO 0000000b 0 Access to EEPROM 0: Do not change 1: Reset RO R/W Note 19 0b Offset: 0502h-0503h Size: 16 bits Bits Description ECAT Type PDI Type Default 15 Busy 0: EEPROM interface is idle 1: EEPROM interface is busy RO RO 0b 14 Error Write Enable 0: No error 1: Write Command without Write enable (See Note 20) RO RO 0b 13 Error Acknowledge/Command 0: No error 1: Missing EEPROM acknowledge or invalid command (See Note 20) Note: EEPROM emulation only: PDI writes 1 if a temporary failure has occurred. RO R/[W] Note 21 0b 12 EEPROM Loading Status 0: EEPROM loaded, device information okay 1: EEPROM not loaded, device information not available (EEPROM loading in-progress or finished with a failure) RO RO 0b 11 Checksum Error in ESC Configuration Area 0: Checksum okay 1: Checksum error RO R/[W] Note 21 0b |
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