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LAN9252/ML データシート(PDF) 267 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 267 Page - Microchip Technology |
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267 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 267 LAN9252 12.14.57 MII MANAGEMENT PDI ACCESS STATE REGISTER Note 33: Write access to the Access to MII Management (PDI) bit of this register is only possible if the Force PDI Access State bit of this register is 0 and the Access to MII Management (ECAT) bit of the MII Management ECAT Access State Register is 0. 12.14.58 PHY PORT STATUS REGISTERS There are 4 8-bit PHY Port Status registers, each with unique address offsets as shown above. The variable “x” is used in the following bit descriptions to represent ports 0-3. Offset: 0517h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:2 RESERVED Write 0. RO RO 000000b 1 Force PDI Access State 0: Do not change Access to MII Management (PDI) bit 1: Reset Access to MII Management (PDI) bit R/W RO 0b 0 Access to MII Management (PDI) 0: ECAT has access to MII management 1: PDI has access to MII management RO R/W Note 33 0b Offset: 0518h-051Bh Port 0: 0518h Port 1: 0519h Port 2: 051Ah Port 3: 051Bh Size: 8 bits Bits Description ECAT Type PDI Type Default 7:6 RESERVED Write as 0. RO RO 00b 5 Port x Lost Link Counter 0: No Update 1: PHY Configuration was Updated Note: Cleared by writing any value to at least one of the PHY Port Status Registers. R/WC Note 34 R/WC Note 34 0b 4 Port x Link Partner Error 0: No Error Detected 1: Link Partner Error RO RO 0b 3 Port x Read Error 0: No Read Error Detected 1: Read Error has Occurred Note: Cleared by writing any value to at least one of the PHY Port Status Registers. R/WC Note 34 R/WC Note 34 0b |
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