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LAN9252/ML データシート(PDF) 285 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 285 Page - Microchip Technology |
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285 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 285 LAN9252 12.14.77 SYNC0 STATUS REGISTER 12.14.78 SYNC1 STATUS REGISTER 12.14.79 START TIME CYCLIC OPERATION REGISTER Note: Writes to this register depend on the Sync Out Unit Control bit of the Cyclic Unit Control Register. It is only writable if Sync Out Unit Control is 0. Note: When the Auto-activation bit of the Activation Register is 1: The upper 32 bits are automatically extended if only the lower 32 bits are written within one frame. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 098Eh Size: 8 bits Bits Description ECAT Type PDI Type Default 7:1 RESERVED RO RO 0000000b 0 SYNC0 State for Acknowledge Mode SYNC0, in Acknowledge Mode, is cleared by reading this regis- ter from PDI. Use only in Acknowledge Mode. RO RO 0b Offset: 098Fh Size: 8 bits Bits Description ECAT Type PDI Type Default 7:1 RESERVED RO RO 0000000b 0 SYNC1 State for Acknowledge Mode SYNC1, in Acknowledge Mode, is cleared by reading this regis- ter from PDI. Use only in Acknowledge Mode. RO RO 0b Offset: 0990h-0997h Size: 64 bits Bits Description ECAT Type PDI Type Default 63:0 Write: Start time (System Time) of cyclic operation in ns. Read: System time of next SYNC0 pulse in ns. R/W R/W 00000000h 00000000h |
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