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LAN9252/ML データシート(PDF) 284 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 284 Page - Microchip Technology |
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284 / 329 page  LAN9252 DS00001909A-page 284 2015 Microchip Technology Inc. 12.14.75 PULSE LENGTH OF SYNCSIGNALS REGISTER Note 39: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu- rable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.76 ACTIVATION STATUS REGISTER Offset: 0982h-0983h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Pulse length of SyncSignals (in units of 10ns) A value of 0 is used for Acknowledge Mode: SyncSignal will be cleared by reading the SYNC0 Status Register/SYNC1 Status Register. RO RO 0000h Note 39 Offset: 0984h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:3 RESERVED RO RO 00000b 2 Start Time Cyclic Operation (Start Time Cyclic Operation Regis- ter) plausibility check result when Sync Out Unit was activated. 0: Start Time was within near future 1: Start Time was out of near future RO RO 0b 1 SYNC1 Activation State 0: First SYNC1 pulse is not pending 1: First SYNC1 pulse is pending RO RO 0b 0 SYNC0 Activation State 0: First SYNC0 pulse is not pending 1: First SYNC0 pulse is pending RO RO 0b |
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