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LAN9252/ML データシート(PDF) 288 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 288 Page - Microchip Technology |
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288 / 329 page  LAN9252 DS00001909A-page 288 2015 Microchip Technology Inc. 12.14.85 LATCH0 STATUS REGISTER 12.14.86 LATCH1 STATUS REGISTER Offset: 09AEh Size: 8 bits Bits Description ECAT Type PDI Type Default 7:3 RESERVED Write as 0. RO RO 00000b 2 LATCH0 Pin State RO RO 0b 1 Event LATCH0 Negative Edge 0: Negative edge not detected or continuous mode 1: Negative edge detected in single event mode only. Note: Flag cleared by reading the LATCH0 Time Negative Edge Register. RO RO 0b 0 Event LATCH0 Positive Edge 0: Positive edge not detected or continuous mode 1: Positive edge detected in single event mode only. Note: Flag cleared by reading the LATCH0 Time Positive Edge Register. RO RO 0b Offset: 09AFh Size: 8 bits Bits Description ECAT Type PDI Type Default 7:3 RESERVED Write as 0. RO RO 00000b 2 LATCH1 Pin State RO RO 0b 1 Event LATCH1 Negative Edge 0: Negative edge not detected or continuous mode 1: Negative edge detected in single event mode only. Note: Flag cleared by reading the LATCH1 Time Negative Edge Register. RO RO 0b 0 Event LATCH1 Positive Edge 0: Positive edge not detected or continuous mode 1: Positive edge detected in single event mode only. Note: Flag cleared by reading the LATCH1 Time Positive Edge Register. RO RO 0b |
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