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Preliminary Technical Data

AD5762R

Rev. PrA | Page 23 of 33

VOUT

DAC

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

VREFIN

SYNC

INPUT

SCLK

Figure 40. Simplified Serial Interface of Input Loading Circuitry

for One DAC Channel

TRANSFER FUNCTION

Table 6 shows the ideal input code to output voltage

relationship for the AD5762R for both offset binary and twos

complement data coding.

Table 6. Ideal Output Voltage to Input Code Relationship for

the AD5762R

Digital Input

Analog Output

Offset Binary Data Coding

MSB

LSB

VOUT

1111

+2 VREFIN × (32767/32768)

1000

0000

0001

+2 VREFIN × (1/32768)

1000

0000

0 V

0111

1111

−2 VREFIN × (1/32768)

0000

−2 VREFIN × (32767/32768)

Twos Complement Data Coding

MSB

LSB

VOUT

0111

1111

+2 VREFIN × (32767/32768)

0000

0001

+2 VREFIN × (1/32768)

0000

0 V

1111

−2 VREFIN × (1/32768)

1000

0000

−2 VREFIN × (32767/32768)

The output voltage expression for the AD5762R is given by

⎥⎦

⎤

⎢⎣

⎡

−

65536

REFIN

OUT

where:

D is the decimal equivalent of the code loaded to the DAC.

VREFIN is the reference voltage applied at the REFA, REFB pins.

ASYNCHRONOUS CLEAR (CLR)

CLR is a negative edge triggered clear that allows the outputs to

be cleared to either 0 V (twos complement coding) or negative

full scale (offset binary coding). It is necessary to maintain CLR

low for a minimum amount of time (see Figure 2) for the

operation to complete. When the CLR signal is returned high,

the output remains at the cleared value until a new value is

programmed. If at power-on CLR is at 0 V, then all DAC

outputs are updated with the clear value. A clear can also be

initiated through software by writing the command 0x04XXXX

to the AD5762R.

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