Preliminary Technical Data

AD5762R

Rev. PrA | Page 25 of 33

DATA REGISTER

The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer

is to take place (see Table 8). The data bits are in positions DB15 to DB0 for the AD5762R as shown in Table 11.

Table 11. Programming the AD5762R Data Register

REG2

REG1

REG0

A2

A1

A0

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

DAC Address

16-Bit DAC Data

COARSE GAIN REGISTER

The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data

transfer is to take place (see Table 8). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC

as shown in Table 13.

Table 12. Programming the AD5762R Coarse Gain Register

REG2

REG1

REG0

A2

A1

A0

DB15 …. DB2

DB1

DB0

0

1

1

DAC Address

Don’t Care

CG1

CG0

Table 13. Output Range Selection

Output Range

CG1

CG0

±10 V (default)

0

0

±10.2564 V

0

1

±10.5263 V

1

0

FINE GAIN REGISTER

The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC channel the data

transfer is to take place (see Table 8). The AD5762R fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC

channel by −32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 14 and Table 15. The adjustment is made to both the positive full-scale

points and the negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos

complement.

Table 14. Programming AD5762R Fine Gain Register

REG2

REG1

REG0

A2

A1

A0

DB15:DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

0

DAC Address

Don’t Care

FG5

FG4

FG3

FG2

FG1

FG0

Table 15. AD5762R Fine Gain Register Options

Gain Adjustment

FG5

FG4

FG3

FG2

FG1

FG0

+31 LSBs

0

1

1

1

1

1

+30 LSBs

0

1

1

1

1

0

-

-

-

-

-

-

No Adjustment (default)

0

0

0

0

0

0

-

-

-

-

-

-

−31 LSBs

1

0

0

0

0

1

−32 LSBs

1

0

0

0

0

0

OFFSET REGISTER

The offset register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC channel the data

transfer is to take place (see Table 8). The AD5762R offset register is an 8-bit register and allows the user to adjust the offset of each

channel by −16 LSBs to +15.875 LSBs in steps of ⅛ LSB as shown in Table 16 and Table 17. The offset register coding is twos complement.

Table 16. Programming the AD5762R Offset Register

REG2

REG1

REG0

A2

A1

A0

DB15:DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

1

DAC Address

Don’t Care

OF7

OF6

OF5

OF4

OF3

OF2

OF1

OF0