SDA

SCL

1

0

0

1

0

0

A0 R/W

1

0

D11 D10

D9 D8 D7 D6 D5 D4

0

D3 D2 D1

D0

0

0

0

0

1

START

TSC2017

ACK

MASTER

ACK

MASTER

NACK

STOPor

Repeated

START

AddressByte

DataByte1

DataByte2

TSC2017

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SBAS472 – DECEMBER 2009

READ A CONVERSION/READ CYCLE

For best performance, the I2C bus should remain in an idle state while an A/D conversion is taking place. This

idling prevents digital clock noise from affecting the bit decisions being made by the TSC2017. The master

should wait for at least 10

μs before attempting to read data from the TSC2017 to realize this best performance.

However, the master does not need to wait for a completed conversion before beginning a read from the slave, if

full 12-bit performance is not necessary.

Data access begins with the master issuing a START condition followed by the address byte (see Table 1) with

R/W = 1.

When the eighth bit has been received and the address matches, the slave issues an acknowledge. The first

byte of serial data then follows (D11-D4, MSB first).

After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge.

The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0,

followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to

indicate that the last data byte has been received. If the master somehow acknowledges the second data byte,

invalid data are returned (FFh). This condition applies to both 12-and 8-bit modes. See Figure 32 for a complete

I2C read transmission.

Figure 32. Complete I2C Serial Read Transmission

Copyright © 2009, Texas Instruments Incorporated

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