TSC2017

SBAS472 – DECEMBER 2009

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THROUGHPUT RATE AND I

2C BUS TRAFFIC

Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is

much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The

throughput is further limited by the I2C bus bandwidth. The effective throughput is approximately 20kSPS at 8-bit

resolution, or 10kSPS at 12-bit resolution. This preprocessing saves a large portion of the I2C bandwidth for the

system to use on other devices.

Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal

4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For VDD = 1.6V, the frequency

reduces to 3.61MHz, which gives a 3.61MHz/16 = 225kSPS raw A/D converter sample rate.

12-Bit Operation

For 12-bit operation, sending the conversion result across the I2C bus takes 49 bus clocks (SCL clock). Each

write cycle takes 20 I2C cycles (START, STOP, address byte, two ACKs, and command byte). Each read cycle

takes 29 I2C cycles (START, STOP, address byte, three ACKs, and data bytes 1 and 2). Seven

sample-and-conversions take 19 x 7 internal clocks to complete. The MAV filter loop requires 19 internal clocks.

For VDD = 1.6V, the complete processed data cycle time calculations are shown in Table 5. Because the first

acquisition cycle overlaps with the I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For

12-bit mode, (19 × 7 + 19) – 4 = 148 CCLKs plus I/O are required.

8-Bit Operation

For 8-bit operation, sending the conversion result across the I2C bus takes 40 bus clocks (SCL clock). Each write

cycle takes 20 I2C cycles (START, STOP, address byte, two ACKs, and command byte). Each read cycle takes

20 I2C cycles (START, STOP, address byte, 2 ACKs, and data byte 1). Seven sample-and-conversions takes 16

x 7 internal clocks to complete. The MAV filter loop requires 19 internal clocks. For VDD = 1.6V, the complete

processed data cycle time calculations are shown in Table 5. Because the first acquisition cycle overlaps with the

I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For 8-bit mode, (16 × 7 + 19) – 4 = 127

CCLKs plus I/O are required.

Table 5. Measurement Cycle Time Calculations

STANDARD MODE: 100kHz (Period = 10

μs)

8-Bit

40 × 10

μs + 127 × 277ns = 435.2μs (2.3kSPS through the I2C bus)

12-Bit

49 × 10

μs + 148 × 555ns = 572.2μs (1.75kSPS through the I2C bus)

FAST MODE: 400kHz (Period = 2.5

μs)

8-Bit

40 × 2.5

μs + 127 × 277ns = 135.2μs (7.4kSPS through the I2C bus)

12-Bit

49 × 2.5

μs + 148 × 555ns = 204.7μs (4.88kSPS through the I2C bus)

HIGH-SPEED MODE: 1.7MHz (Period = 588ns)

8-Bit

40 × 588ns + 127 × 277ns = 58.7

μs (17.03kSPS through the I2C bus)

12-Bit

49 × 588ns + 148 × 555ns = 111

μs (9.01kSPS through the I2C bus)

HIGH-SPEED MODE: 3.4MHz (Period = 294ns)

8-Bit

40 × 294ns + 127 × 277ns = 46.9

μs (21.3kSPS through the I2C bus)

12-Bit

49 × 294ns + 148 × 555ns = 96.6

μs (10.35kSPS through the I2C bus)

As an example, use VDD = 1.6V and 12-bit mode with the Fast-mode I

2C clock (f

SCL = 400kHz). The equivalent

TSC throughput is at least seven times faster than the effective throughput across the bus (4.88k x 7 =

34.19kSPS). The supply current to the TSC for this rate and configuration is 145

μA. To achieve an equivalent

sample throughput of 8.2kSPS using the device without preprocessing, the TSC2017 consumes only (8.2/34.19)

× 145

μA = 34.7μA.

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