L9945 datasheet(99/144 Pages) STMICROELECTRONICS

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RESPONSE 10

Frame partitioning

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Description:

BIST & HWSC result and device status

Note:

the value of DIS, NDIS and EN6 related bit depends on how the microcontroller drives such pins. The value of

POR and NRES related bit depends on which event caused the logic reset. The value of BIST and HWSC

related bit depends on which event caused the logic reset: self test sequence is not performed in case of POR.

In addition, the value of BIST_DONE and HWSC_DONE bit depends on the status of self test sequence at the

time instant where the read event occurs. The CC_LATCH is set in case the first SPI communication occurs

after the watchdog timer expired. The UV_DIS_LATCH and UV_VDD5_LATCH might be set at startup,

depending on the VDD5 ramp slope. It is strongly recommended to perform two consecutive SPI read via

COMMAND 10 in order to verify that the relevant faults (eventually latched during startup) are cleared.

[31:28] C: Response to command 10

Reset: 1010

Reset Condition: -

[27] R/W: Bit to read/write configuration

0: Write & request read

1: Request read only

Reset: 1

Reset Condition: POR, NRES

[26] EN6_LATCH: Shows if a deactivation via EN6 pin was detected since last read out (EN6 = LOW)

0: no disable via EN6 detected

1: disable via EN6 detected

Reset: X

Reset Condition: Read out POR

[25] EN6_STATE: Shows if channel 6 is currently disabled by the EN6 input

0: EN disabled

1: EN enabled

Reset: 0

Reset Condition: -

[24] OV_DIS_LATCH: Bit set to 1 (OV filtering expired) if VDD5 overvoltage disable was triggered since last read out (shows also if

OV occurs during Reset)

0: no OV disable condition detected

1: OV disable condition detected

Reset: 0

Reset Condition: -

L9945

Functional description

DS12275 - Rev 10

page 99/144

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