 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
L9945 データシート(PDF) 27 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L9945 データシート(HTML) 27 Page - STMicroelectronics |
|
|
27 / 144 page  Note: Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. A current flowing out of the device has minus (-) sign; a current flowing into the device has plus (+) sign. Charge currents turn ON the NMOS and OFF the PMOS. Discharge currents turn OFF the NMOS and ON the PMOS. Table 15. Output pre-driver stages electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit VGNSP -VSNGP Gate Output voltage (Reversed for PMOS) - 10 - 14 V ICh3Gx Gate charge current NMOS GCC[1:0] = [1, 1] -1.88 - -1.1 mA Gate charge current PMOS -1.85 - -0.55 mA ICh2Gx Gate charge current NMOS and PMOS GCC[1:0] = [1, 0] -8.6 - -4 mA ICh1Gx Gate charge current NMOS and PMOS GCC[1:0] = [0, 1] -32.4 - -19.6 mA ICh0Gx Gate charge current NMOS GCC[1:0] = [0, 0] -100 - -40 mA Gate charge current PMOS -77 - -43.5 mA IDCh3Gx Gate discharge current NMOS and PMOS GCC[1:0] = [1, 1] 0.75 - 1.9 mA IDCh2Gx Gate discharge current NMOS and PMOS GCC[1:0] = [1, 0] 3.8 - 7.4 mA IDCh1Gx Gate discharge current NMOS and PMOS GCC[1:0] = [0, 1] 16.8 - 27.4 mA IDCh0Gx Gate discharge current NMOS and PMOS GCC[1:0] = [0, 0] 55 - 101 mA Tsw_GC Delay to switch from GCC[a,b] to GCC[c,d] - - - 0.1 µs Ipeak Minimum peak current capability VPS > 7.5V Tested at VPS > 7.5 V and output shorted to GND 40 - - mA CLOAD Equivalent capacitive load to be driven - 0.1 - - nF td_OFF Turn ON/OFF delay 50% NONx to 50% OFF gate current test condition: 0.1 nF checked for LS/HS config (switch) - - 1.5 μs td_ON Turn OFF/ON delay 50% NONx to 50% ON gate current test condition: 0.1 nF checked for LS/HS config (switch) - - 1.5 μs ICR_CON Pre-driver Cross conduction current guaranteed by design - - 2 mA ILEAK_Gx GNSPx leakage current in tristate GNSP-SNGP voltage requirements < 20 V in case of external P-channel (Gate to SNGPx) -10 - 10 µA IDRNx DRNx input leakage current POR or NRES active; V_DRNx = 0 V to 28 V -10 - 10 µA ILEAK_S SNGPx input leakage current POR or NRES active or Normal mode; V_SNGPx = 0 V to 28 V -10 - 10 µA VGNSP-VSNGP GNSP to SNGP voltage when OFF gate current is on - - - 100 mV 5.5 H-Bridge The pre-drivers can be configured into two independent H-Bridges. In this configuration Channels 1-4 are used for H-Bridge 1, while Channels 5-8 are used for H-bridge 2. The device can handle up to two H-bridge. There are two possible configurations which can co-exist: • H-Bridge 1: it involves channels 1 (HS), 2 (HS), 3 (LS) and 4 (LS) and can be activated by setting HB1_config = 1 • H-Bridge 2: it involves channels 5 (HS), 6 (HS), 7 (LS) and 8 (LS) and can be activated by setting HB2_config = 1 Configurations above are automatically applied once the HBx_config bit is set. The N_P_config_xx bit set the MOSFET type (NMOS, PMOS) used in the H-bridge high-side. For H-bridge 2, EN6 must be set high to enable channel 6. L9945 Functional description DS12275 - Rev 10 page 27/144 |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
