D950-CORE datasheet(80/89 Pages) STMICROELECTRONICS

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D950-Core

edge) to an interrupt input (ITRQi).

•

DIP_ENA = 1, the number of available interrupt sources in the interrupt

controller is low: Connect the logical AND of the DITi signals (DIT_AND) to a

single interrupt input (ITRQi), the interrupt pending bits (DIPi) of the DAIC

interrupt. (see 7.4.4).

7.4.4 DMA Peripheral Registers

Address Registers

Two 16-bit registers (unsigned) are dedicated per channel for transfer address:

•

DIA: initial address. This register contains the initial address of the selected

address bus (see DBC-bit of DGC).

•

DCA: current address. This register contains the value to be transferred to the

selected address bus (see

DBC-bit of DGC) during the next transfer. The

different DCA values are:

Note:

See DAIC register for DAI and DLA definitions

Counting Registers

Two 16-bit registers (unsigned) per channel are dedicated for transfer count.

For a transfer of a N data block, DIC and DCC registers have to be loaded with N-1.

When DCC content is 0 (valid transfer count), it is loaded with DIC content for the next transfer.

•

DIC: initial count. This register contains the total number of transfers of the

entire block

•

DCC: current count. This register contains the remaining number of transfers

to be done to fill the entire block. It is decremented after each transfer. The

DCC values are:

RESET

DAI

DLA

DCC = 0

DCA(n+1)

DCA(n)

DCA(n) + 1

DIA

RESET

DCC = 0

DCA(n+1)

DCA(n) - 1

DIC

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