LM2507GR datasheet(18/22 Pages) NSC

部品番号	LM2507GR

部品情報	Low Power Mobile Pixel Link (MPL) Level 0, 16-bit CPU Display interface Serializer and Deserializer

PDF	22 Pages

Scroll/Zoom	100%

メーカー	NSC [National Semiconductor (TI)]

ホームページ	http://www.national.com

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18 / 22 page

Application Information (Continued)

DISPLAY APPLICATION

The LM2507 chipset is intended for interfacing between a

host (processor) and a Display. It supports a 16, 9 or 8-bit i80

CPU style interfaces and can be configured as shown in

Figure 19. The Display side parallel bus may be connected

to one or two displays. Each display has its own chipselect

signal. The multidrop bus should be laid out to minimize any

resulting stub lengths.

If only one display is required, the unused CS* master input

must be tied off (High, disabled). The unused CS* slave

output should be left as a no-connect (NC).

If a 8-bit or 9-bit CPU bus width is desired, the unused

master inputs must be tied off (connect to Ground). The

unused Slave outputs should be left as no-connects.

20186062

FIGURE 18. MPL Interface Layout – microArray to LLP Package

20186001

FIGURE 19. CPU Mode Display Interface Application

LM2507GR データシート(PDF) 18 Page - National Semiconductor (TI)