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LM2507GR データシート(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 LM2507GR
部品情報  Low Power Mobile Pixel Link (MPL) Level 0, 16-bit CPU Display interface Serializer and Deserializer
PDF  22 Pages
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM2507GR データシート(HTML) 3 Page - National Semiconductor (TI)

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Pin Descriptions — CPU (Continued)
Pin Name
No.
of Pins
I/O, Type
Description
CPU Master
(MST)
CPU Slave
(SLV)
POWER/GROUND PINS
V
DDA
1
Power
Power Supply Pin for the MST PLL and MPL Interface. 1.74V to 2.0V
V
SSA
1
Ground
Ground Pin for the MPL Interface, and analog circuitry.
V
DDcore
1
Power
Power Supply Pin for the digital core. 1.74V to 2.0V
V
SScore
1
Ground
Ground Pin for the digital core.
V
DDIO
2
Power
Power Supply Pin for the parallel interface I/Os. 1.74V to 3.0V
V
SSIO
2
Ground
Ground Pin for the parallel interface I/Os.
V
bulk
9
Connect to Ground - uArray Package
DAP
1
Connect to Ground - LLP Package
Note:
I = Input, O = Output, IO = Input/Output. Do not float input pins.
Ordering Information
NSID
Package Type
Package ID
LM2507GR
49L MicroArray, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch
GRA49A
LM2507SQ
40L LLP, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch
SQF40A
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