LM2507GR datasheet(8/22 Pages) NSC

8 / 22 page

Functional Description (Continued)

OFF PHASE

In the OFF phase, both Master and Slave MPL transmitters

are turned off with zero current flowing on the MC and MDn

lines. Figure 7 shows the transition of the MPL bus into the

OFF phase. If an MPL line is driven to a logical Low (high

current) when the OFF phase is entered it may temporarily

pass through as a logical High (low current) before reaching

the zero line current state.

The link may be powered down by asserting both the Mas-

ter’s and Slave’s PD* input pins (Low). This causes the

devices to immediately put the link to the OFF Phase and

internally enter a low power state. To avoid loss of data the

Master’s PD* input should only be asserted after the MPL

bus has been in the IDLE state for at least 20 MC clock

cycles. This gives the Slave enough time to complete any

write operations received from the MPL bus.

CPU INTERFACE COMPATIBILITY

The CPU i80 Interface provides compatibility between a

CPU Interface host and a small form factor (SFF) Display or

other fixed I/O port application.

WRITE TRANSACTION

The WRITE transaction consists of one MC cycle of control

information followed by four MC cycles of write data for a

16-bit WRITE. Since WRITE transactions transfer informa-

tion on both edges of MC it takes five MC cycles to complete

a write transaction. The MD0 line carries the Start bit (Low),

the A/D (Address/Data) bit and then the data payload of 8

bits (D0-7). The MD1 line carries the R/W* bit (Read/Write*),

the CS1/2 bit and then the data payload of 8 bits (D8-15).

The data payload is sent least significant bit (LSB) first. The

CS1/2 bit denotes which Chipset pin was active. CS1/2 =

HIGH designates that CS1* is active (Low). CS1/2 = LOW

designates that CS2* is active (Low). CS1* and CS2* LOW

is not allowed.

8-bit and 9-bit CPU bus widths may be supported by tieing

off unused inputs.

20186005

FIGURE 6. Bus Power Up Timing

20186006

FIGURE 7. Bus Power Down Timing

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