LM2507GR datasheet(13/22 Pages) NSC

13 / 22 page

Functional Description (Continued)

TABLE 3. READ — i80 CPU Interface Parameters

No.

Parameter

Min

Typ

Max

Units

MasterIN

Set Up Time (A/D, RD*) and Data On Time

3.5

MasterIN

Hold Time (A/D, RD*) and Data Off Time

2.5

Master

Master Latency

MC Cycles

Slave

Slave Latency

MC Cycles

Slave

Read* Delay

MC Cycles

Slave

Read Low Pulse Width

MC Cycles

Slave

Data Set Up Time

Slave

Data Hold Time

Slave

Slave Read Latency

MC Cycles

T10

Master

MST Read Latency and INTR Delay

MC Cycles

T11

Master

Data Delay

T12

MasterOUT

Data Valid after Strobe

7.5

T13

MasterOUT

RD* active pulse width

>50

T14

MasterOUT

INTR De-assert

MC Cycles

T15

MasterOUT

Recovery Time, (Note 9)

T16

MasterOUT

INTR Response

MC Cycles

T17

Slave

IDR Delay, IDR = High, Figure 13

MC Cycles

SLAVE OUTPUT TIMING

The Slave output recreates the transaction that was sent to

the Master. However exact timing of the Slave output is not

identical to the Master input. The active pulse (WR* and RD*

output pulse) is a function of the MC cycle rate alone. The

width applied on the Master input (assuming it meets set and

hold requirements), is not regenerated by the Slave output.

Also with WRITE transactions the output state is held until

the next transaction requires them to be updated. For ex-

ample after a i80 WRITE to CS1*, the A/D, DATAn, and CS1*

output will remain static and hold their last state. CS1* will

remain Low until a transaction to CS2* or a PowerDown

event. This is acceptable to the target device as normally

both an active CS and RD or WR signal is required.

On the display side, the Slave can be configured through the

IDR input to issue one or two read transactions to the

peripheral. If configured for two read transactions, it will take

longer for the INTR signal to be asserted from the Master to

account for the time taken for the remote dummy read. Use

of this mode allows for consistent behavior from the periph-

eral regardless of the use of the MPL link (LM2507) or not.

See Figure 13.

Compatibility of target device’s timing requirements should

be checked. Check that the active pulse is wide enough for

the current settings. If the SLV output is too fast, a slower MC

rate should be chosen (use a lower input CLK frequency).

20186034

FIGURE 13. Slave Output Timing with IDR = H

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