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74LVC2G240DP データシート(PDF) 4 Page - Nexperia B.V. All rights reserved |
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74LVC2G240DP データシート(HTML) 4 Page - Nexperia B.V. All rights reserved |
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4 / 22 page ![]() 74LVC2G240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 — 8 April 2013 4 of 22 NXP Semiconductors 74LVC2G240 Dual inverting buffer/line driver; 3-state 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Fig 5. Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-2 001aam590 74LVC2G240 Transparent top view 8 7 6 5 1 2 3 4 1OE 1A 2Y GND VCC 2OE 1Y 2A 001aaf077 1A 1Y 1OE 2Y 2OE 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC2G240 Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 SOT902-2 1OE 1 7 output enable input 1OE (active LOW) 1A 2 6 data input 2Y 3 5 data output GND 4 4 ground (0 V) 2A 5 3 data input 1Y 6 2 data output 2OE 7 1 output enable input 2OE (active LOW) VCC 8 8 supply voltage Table 4. Function table[1] Input Output nOE nA nY LLH LH L HX Z |
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