74LVC2G240

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Product data sheet

Rev. 8 — 8 April 2013

8 of 22

NXP Semiconductors

74LVC2G240

Dual inverting buffer/line driver; 3-state

11. Dynamic characteristics

[1]

Typical values are measured at nominal VCC and at Tamb = 25 C.

[2]

tpd is the same as tPLH and tPHL

[3]

ten is the same as tPZH and tPZL

[4]

tdis is the same as tPLZ and tPHZ

[5]

CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(C

L  VCC

2

 f

o) = sum of outputs.

Table 8.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ[1]

Max

Min

Max

tpd

propagation delay

nA to nY; see Figure 7

[2]

VCC = 1.65 V to 1.95 V

1.0

4.1

9.5

1.0

11.9

ns

VCC = 2.3 V to 2.7 V

0.5

2.6

5.2

0.5

6.5

ns

VCC = 2.7 V

1.0

3.0

5.5

1.0

6.9

ns

VCC = 3.0 V to 3.6 V

0.5

2.5

4.6

0.5

5.8

ns

VCC = 4.5 V to 5.5 V

0.5

2.0

4.0

0.5

5.0

ns

ten

enable time

nOE to nY; see Figure 8

[3]

VCC = 1.65 V to 1.95 V

1.5

4.5

10.3

1.5

12.9

ns

VCC = 2.3 V to 2.7 V

1.0

2.9

5.6

1.0

7.0

ns

VCC = 2.7 V

1.5

3.4

5.6

1.5

7.0

ns

VCC = 3.0 V to 3.6 V

0.5

2.5

4.7

0.5

5.9

ns

VCC = 4.5 V to 5.5 V

0.5

2.0

3.8

0.5

4.8

ns

tdis

disable time

nOE to nY; see Figure 8

[4]

VCC = 1.65 V to 1.95 V

1.0

3.5

11.6

1.0

14.1

ns

VCC = 2.3 V to 2.7 V

0.5

1.9

5.8

0.5

7.6

ns

VCC = 2.7 V

1.0

2.8

4.5

1.0

5.8

ns

VCC = 3.0 V to 3.6 V

1.0

2.7

4.4

1.0

5.7

ns

VCC = 4.5 V to 5.5 V

0.5

1.9

3.4

0.5

4.6

ns

CPD

power dissipation

capacitance

per buffer; VI = GND to VCC

[5]

output enabled

-

18

-

-

-

pF

output disabled

-

5

-

-

-

pF