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ST10R172L データシート(PDF) 44 Page - STMicroelectronics |
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ST10R172L データシート(HTML) 44 Page - STMicroelectronics |
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44 / 68 page ![]() 44/68 ST10R172L - ELECTRICAL CHARACTERISTICS Data hold after RD rising edge t18 SR 0 –0 – ns Data float after RD rising edge 12)) t19 SR – 15 + tF 2 – 2TCL - 5 + tF 2 ns Data valid to WR t22 CC 13 + tC – 2TCL - 7 + tC –ns Data hold after WR t23 CC 13 + tF – 2TCL - 7+ tF –ns ALE rising edge after RD, WR t25 CC 10 + tF – 2TCL - 10 + tF –ns Address hold after RD, WR t27 CC 10 + tF – 2TCL - 10 + tF –ns Latched CS setup to ALE t38 CC -7 + tA 3 + tA -7 + tA 3 + tA ns Unlatched CS setup to ALE t38u CC 3 + tA – TCL - 7 + tA –ns Latched CS low to Valid Data In t39 SR – 13 + tC + 2tA – 3TCL - 17 + tC + 2tA ns Unlatched CS low to Valid Data In t39u SR – 23 + tC + 2tA – 4TCL - 17 + tC + 2tA ns Latched CS hold after RD, WR t40 CC 20 + tF – 3TCL - 10 + tF –ns Unlatched CS hold after RD, WR t40u CC 10 + tF – 2TCL - 10 + tF –ns ALE fall. edge to RdCS, WrCS (with RW delay) t42 CC 7 + tA – TCL - 3 + tA –ns ALE fall. edge to RdCS, WrCS (no RW delay) t43 CC -3 + tA – -3 + tA –ns Address float after RdCS (with RW delay)1 t44 CC – 31 – 31 ns Address float after RdCS (no RW delay)1 t45 CC – 131 – TCL + 31 ns Parameter Symbol Max. CPU Clock = 50 MHz Variable CPU Clock 1/2TCL = 1 to 50 MHz min. max. min. max. Table 14 Multiplexed bus 1 |
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