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M306V2EEFS データシート(PDF) 76 Page - Renesas Technology Corp |
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M306V2EEFS データシート(HTML) 76 Page - Renesas Technology Corp |
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76 / 271 page  Rev.1.40 Oct 06, 2004 page 76 of 269 M306V2ME-XXXFP, M306V2EEFP Single-chip mode Memory expansion mode Transfer unit Bus width Access address Microprocessor mode No. of read No. of write No. of read No. of write cyclescyclescyclescycles 16-bit Even 1 1 1 1 8-bit transfers (BYTE= “L”) Odd 1 1 1 1 (DMBIT= “1”) 8-bit Even — — 1 1 (BYTE = “H”) Odd — — 1 1 16-bit Even 1 1 1 1 16-bit transfers (BYTE = “L”) Odd 2 2 2 2 (DMBIT= “0”) 8-bit Even — — 2 2 (BYTE = “H”) Odd — — 2 2 Table 2.9.2 No. of DMAC transfer cycles 2.9.2 DMAC Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 2.9.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k Internal memory External memory Internal ROM/RAM Internal ROM/RAM SFR area Separate busSeparate bus Multiplex /OSD RAM bus No wait With wait No wait With wait 1 2 212 3 Coefficient j, k |
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